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ARM64架构主要内容：

ContentsARM Architecture Reference Manual ARMv8, forARMv8-A architecture profilePart A ARMv8 Architecture Introduction and OverviewChapter A1 Introduction to the ARMv8 Architecture    A1.1 About the ARM architecture     A1.2 Architecture profiles    A1.3 ARMv8 architectural concepts    A1.4 Supported data types    A1.5 Floating-point and Advanced SIMD support    A1.6 Cryptographic Extension    A1.7 The ARM memory modelPart B The AArch64 Application Level ArchitectureChapter B1 The AArch64 Application Level Programmers’ Model    B1.1 About the Application level programmers’ model    B1.2 Registers in AArch64 Execution state    B1.3 Software control features and EL0Chapter B2 The AArch64 Application Level Memory Model    B2.1 Address space    B2.2 Memory type overview    B2.3 Caches and memory hierarchy    B2.4 Alignment support    B2.5 Endian support    B2.6 Atomicity in the ARM architecture    B2.7 Memory ordering    B2.8 Memory types and attributes    B2.9 Mismatched memory attributes    B2.10 Synchronization and semaphoresPart C The AArch64 Instruction SetChapter C1 The A64 Instruction Set    C1.1 Introduction    C1.2 Structure of the A64 assembler language    C1.3 Address generation    C1.4 Instruction aliasesChapter C2 About the A64 Instruction Descriptions    C2.1 Understanding the A64 instruction descriptions    C2.2 Conventions used in AArch64 instruction and System register descriptionsChapter C3 A64 Instruction Set Overview    C3.1 Branches, Exception generating, and System instructions    C3.2 Loads and stores    C3.3 Data processing - immediate    C3.4 Data processing - register    C3.5 Data processing - SIMD and floating-pointChapter C4 A64 Instruction Set Encoding    C4.1 A64 instruction index by encoding    C4.2 Data processing - immediate    C4.3 Branches, exception generating and system instructions    C4.4 Loads and stores    C4.5 Data processing - register    C4.6 Data processing - SIMD and floating pointChapter C5 The A64 System Instruction Class    C5.1 The System instruction class encoding space    C5.2 Special-purpose registers    C5.3 A64 system instructions for cache maintenance    C5.4 A64 system instructions for address translation    C5.5 A64 system instructions for TLB maintenanceChapter C6 A64 Base Instruction Descriptions    C6.1 Introduction    C6.2 Register size    C6.3 Use of the PC    C6.4 Use of the stack pointer    C6.5 Condition flags and related instructions    C6.6 Alphabetical list of instructionsChapter C7 A64 Advanced SIMD and Floating-point Instruction Descriptions    C7.1 Introduction    C7.2 About the SIMD and floating-point instructions    C7.3 Alphabetical list of floating-point and Advanced SIMD instructionsPart D The AArch64 System Level ArchitectureChapter D1 The AArch64 System Level Programmers’ Model    D1.1 Exception levels    D1.2 Exception terminology    D1.3 Execution state    D1.4 Security state    D1.5 Virtualization    D1.6 Registers for instruction processing and exception handling    D1.7 Process state, PSTATE    D1.8 Program counter and stack pointer alignment    D1.9 Reset    D1.10 Exception entry    D1.11 Exception return    D1.12 The Exception level hierarchy    D1.13 Synchronous exception types, routing and priorities    D1.14 Asynchronous exception types, routing, masking and priorities    D1.15 Configurable instruction enables and disables, and trap controls    D1.16 System calls    D1.17 Mechanisms for entering a low-power state    D1.18 Self-hosted debug    D1.19 The Performance Monitors Extension    D1.20 Interprocessing    D1.21 The effect of implementation choices on the programmers’ modelChapter D2 AArch64 Self-hosted Debug    D2.1 About debug exceptions    D2.2 The debug exception enable controls    D2.3 Routing debug exceptions    D2.4 Enabling debug exceptions from the current Exception level and Security state    D2.5 The effect of powerdown on debug exceptions    D2.6 Summary of the routing and enabling of debug exceptions    D2.7 Pseudocode description of debug exceptions    D2.8 Software Breakpoint Instruction exceptions    D2.9 Breakpoint exceptions    D2.10 Watchpoint exceptions    D2.11 Vector Catch exceptions    D2.12 Software Step exceptions    D2.13 Synchronization and debug exceptionsChapter D3 The AArch64 System Level Memory Model    D3.1 About the memory system architecture    D3.2 Address space    D3.3 Mixed-endian support    D3.4 Cache support    D3.5 External aborts    D3.6 Memory barrier instructions    D3.7 Pseudocode description of general memory system instructionsChapter D4 The AArch64 Virtual Memory System Architecture    D4.1 About the Virtual Memory System Architecture (VMSA)    D4.2 The VMSAv8-64 address translation system    D4.3 VMSAv8-64 translation table format descriptors    D4.4 Access controls and memory region attributes    D4.5 MMU faults    D4.6 Translation Lookaside Buffers (TLBs)    D4.7 TLB maintenance requirements and the TLB maintenance instructions    D4.8 Caches in a VMSA implementationChapter D5 The Performance Monitors Extension    D5.1 About the Performance Monitors    D5.2 Accuracy of the Performance Monitors    D5.3 Behavior on overflow    D5.4 Attributability    D5.5 Effect of EL3 and EL2    D5.6 Event filtering    D5.7 Performance Monitors and Debug state    D5.8 Counter enables    D5.9 Counter access    D5.10 Events, Event numbers and mnemonics    D5.11 Performance Monitors Extension registersChapter D6 The Generic Timer in AArch64 state    D6.1 About the Generic Timer in AArch64 stateChapter D7 AArch64 System Register Descriptions    D7.1 About the AArch64 System registers    D7.2 General system control registers    D7.3 Debug registers    D7.4 Performance Monitors registers    D7.5 Generic Timer registersPart E The AArch32 Application Level ArchitectureChapter E1 The AArch32 Application Level Programmers’ Model    E1.1 About the Application level programmers’ model    E1.2 Additional information about the programmers’ model in AArch32 state    E1.3 Advanced SIMD and floating-point instructions    E1.4 Conceptual coprocessor support    E1.5 ExceptionsChapter E2 The AArch32 Application Level Memory Model    E2.1 Address space    E2.2 Memory type overview    E2.3 Caches and memory hierarchy    E2.4 Alignment support    E2.5 Endian support    E2.6 Atomicity in the ARM architecture    E2.7 Memory ordering    E2.8 Memory types and attributes    E2.9 Mismatched memory attributes    E2.10 Synchronization and semaphoresPart F The AArch32 Instruction SetsChapter F1 The AArch32 Instruction Sets Overview    F1.1 Support for instructions in different versions of the ARM architecture    F1.2 Unified Assembler Language    F1.3 Branch instructions    F1.4 Data-processing instructions    F1.5 PSTATE and banked register access instructions    F1.6 Load/store instructions    F1.7 Load/store multiple instructions    F1.8 Miscellaneous instructions    F1.9 Exception-generating and exception-handling instructions    F1.10 Coprocessor instructions    F1.11 Advanced SIMD and floating-point load/store instructions    F1.12 Advanced SIMD and floating-point register transfer instructions    F1.13 Advanced SIMD data-processing instructions    F1.14 Floating-point data-processing instructionsChapter F2 About the T32 and A32 Instruction Descriptions    F2.1 Format of instruction descriptions    F2.2 Standard assembler syntax fields    F2.3 Conditional execution    F2.4 Shifts applied to a register    F2.5 Memory accesses    F2.6 Encoding of lists of general-purpose registers and the PC    F2.7 About the T32 and A32 instruction encodings    F2.8 Additional pseudocode support for instruction descriptionsChapter F3 T32 Base Instruction Set Encoding    F3.1 Top level T32 instruction set encoding    F3.2 16-bit T32 instruction encoding    F3.3 32-bit T32 instruction encodingChapter F4 A32 Base Instruction Set Encoding    F4.1 Top level A32 instruction set encoding    F4.2 Data-processing and miscellaneous instructions    F4.3 Load/Store Word, Unsigned Byte (immediate, literal)    F4.4 Load/Store Word, Unsigned Byte (register)    F4.5 Media instructions    F4.6 Branch, branch with link, and block data transfer    F4.7 Coprocessor instructions, and Supervisor Call    F4.8 Unconditional instructionsChapter F5 T32 and A32 Instruction Sets Advanced SIMD and floating-point Encodings    F5.1 Overview    F5.2 Advanced SIMD and floating-point instruction syntax    F5.3 Register encoding    F5.4 Advanced SIMD data-processing instructions    F5.5 Floating-point data-processing instructions    F5.6 Advanced SIMD and floating-point register load/store instructions    F5.7 Advanced SIMD element or structure load/store instructions    F5.8 8, 16, and 32-bit transfers accessing the SIMD and floating-point register file    F5.9 64-bit transfers accessing the SIMD and floating-point register fileChapter F6 T32 and A32 Base Instruction Set Instruction Descriptions    F6.1 Alphabetical list of T32 and A32 base instruction set instructions    F6.2 Encoding and use of Banked register transfer instructionsChapter F7 T32 and A32 Advanced SIMD and floating-point Instruction Descriptions    F7.1 Alphabetical list of floating-point and Advanced SIMD instructionsPart G The AArch32 System Level ArchitectureChapter G1 The AArch32 System Level Programmers’ Model    G1.1 About the AArch32 System level programmers’ model    G1.2 Exception levels    G1.3 Exception terminology    G1.4 Execution state    G1.5 Instruction Set state    G1.6 Security state    G1.7 Virtualization    G1.8 AArch32 PE modes, and general-purpose and Special-purpose registers    G1.9 Process state, PSTATE    G1.10 Instruction set states    G1.11 Handling exceptions that are taken to an Exception level using AArch32    G1.12 Exception return to an Exception level using AArch32    G1.13 Asynchronous exception behavior for exceptions taken from AArch32 state    G1.14 AArch32 state exception descriptions    G1.15 Reset into AArch32 state    G1.16 Mechanisms for entering a low-power state    G1.17 The conceptual coprocessor interface and system control    G1.18 Advanced SIMD and floating-point support    G1.19 Configurable instruction enables and disables, and trap controlsChapter G2 AArch32 Self-hosted Debug    G2.1 About debug exceptions    G2.2 The debug exception enable controls    G2.3 Routing debug exceptions    G2.4 Enabling debug exceptions from the current Privilege level and Security state    G2.5 The effect of powerdown on debug exceptions    G2.6 Summary of permitted routing and enabling of debug exceptions    G2.7 Pseudocode description of debug exceptions    G2.8 Software Breakpoint Instruction exceptions    G2.9 Breakpoint exceptions    G2.10 Watchpoint exceptions    G2.11 Vector Catch exceptions    G2.12 Synchronization and debug exceptionsChapter G3 The AArch32 System Level Memory Model    G3.1 About the memory system architecture    G3.2 Address space    G3.3 Mixed-endian support    G3.4 AArch32 cache and branch predictor support    G3.5 System register support for IMPLEMENTATION DEFINED memory features G3-3975    G3.6 External aborts    G3.7 Memory barrier instructions    G3.8 Pseudocode description of general memory system instructionsChapter G4 The AArch32 Virtual Memory System Architecture    G4.1 Execution privilege, Exception levels, and AArch32 Privilege levels    G4.2 About VMSAv8-32    G4.3 The effects of disabling address translation stages on VMSAv8-32 behavior G4-4000    G4.4 Translation tables    G4.5 The VMSAv8-32 Short-descriptor translation table format    G4.6 The VMSAv8-32 Long-descriptor translation table format    G4.7 Memory access control    G4.8 Memory region attributes    G4.9 Translation Lookaside Buffers (TLBs)    G4.10 TLB maintenance requirements    G4.11 Caches in VMSAv8-32    G4.12 VMSAv8-32 memory aborts    G4.13 Exception reporting in a VMSAv8-32 implementation    G4.14 Address translation instructions    G4.15 About the System registers for VMSAv8-32    G4.16 Organization of the CP14 registers in VMSAv8-32    G4.17 Organization of the CP15 registers in VMSAv8-32    G4.18 Functional grouping of VMSAv8-32 System registers    G4.19 Pseudocode description of VMSAv8-32 memory system operationsChapter G5 The Generic Timer in AArch32 state    G5.1 About the Generic Timer in AArch32 stateChapter G6 AArch32 System Register Descriptions    G6.1 About the AArch32 System registers    G6.2 General system control registers    G6.3 Debug registers    G6.4 Performance Monitors registers    G6.5 Generic Timer registersPart H External DebugChapter H1 Introduction to External Debug    H1.1 Introduction to external debug    H1.2 External debugChapter H2 Debug State    H2.1 About Debug state    H2.2 Halting the PE on debug events    H2.3 Entering Debug state    H2.4 Behavior in Debug state    H2.5 Exiting Debug stateChapter H3 Halting Debug Events    H3.1 Introduction to Halting debug events    H3.2 Halting Step debug events    H3.3 Halt Instruction debug event    H3.4 Exception Catch debug event    H3.5 External Debug Request debug event    H3.6 OS Unlock Catch debug event    H3.7 Reset Catch debug events    H3.8 Software Access debug event    H3.9 Synchronization and Halting debug eventsChapter H4 The Debug Communication Channel and Instruction Transfer Register    H4.1 Introduction    H4.2 DCC and ITR registers    H4.3 DCC and ITR access modes    H4.4 Flow control of the DCC and ITR registers    H4.5 Synchronization of DCC and ITR accesses    H4.6 Interrupt-driven use of the DCC    H4.7 Pseudocode description of the operation of the DCC and ITR registersChapter H5 The Embedded Cross-Trigger Interface    H5.1 About the Embedded Cross-Trigger (ECT)    H5.2 Basic operation on the ECT    H5.3 Cross-triggers on a PE in an ARMv8 implementation    H5.4 Description and allocation of CTI triggers    H5.5 CTI registers programmers’ model    H5.6 ExamplesChapter H6 Debug Reset and Powerdown Support    H6.1 About Debug over powerdown    H6.2 Power domains and debug    H6.3 Core power domain power states    H6.4 Emulating low-power states    H6.5 Debug OS Save and Restore sequences    H6.6 Reset and debugChapter H7 The Sample-based Profiling Extension    H7.1 Sample-based profilingChapter H8 About the External Debug Registers    H8.1 Relationship between external debug and System registers    H8.2 Supported access sizes    H8.3 Synchronization of changes to the external debug registers    H8.4 Memory-mapped accesses to the external debug interface    H8.5 External debug interface register access permissions    H8.6 External debug interface registers    H8.7 Cross-trigger interface registers    H8.8 External debug register resetsChapter H9 External Debug Register Descriptions    H9.1 Introduction    H9.2 Debug registers    H9.3 Cross-Trigger Interface registersPart I Memory-mapped Components of the ARMv8 ArchitectureChapter I1 System Level Implementation of the Generic Timer    I1.1 About the Generic Timer specification    I1.2 Memory-mapped counter module    I1.3 Counter module control and status register summary    I1.4 Memory-mapped timer components    I1.5 The CNTBaseN and CNTEL0BaseN frames    I1.6 The CNTCTLBase frame    I1.7 Providing a complete set of counter and timer features    I1.8 Gray-count scheme for timer distribution schemeChapter I2 Recommended Memory-mapped Interfaces to the Performance Monitors    I2.1 About the memory-mapped views of the Performance Monitors registersChapter I3 Memory-Mapped System Control Register Descriptions    I3.1 About the memory-mapped system control register descriptions    I3.2 Performance Monitors memory-mapped registers summary    I3.3 Performance Monitors memory-mapped register descriptions    I3.4 Generic Timer memory-mapped registers overview    I3.5 Generic Timer memory-mapped register descriptionsPart J Architectural PseudocodeChapter J1 ARMv8 Pseudocode    J1.1 Pseudocode for AArch64 operations    J1.2 Pseudocode for AArch32 operation    J1.3 Shared pseudocode

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